Building FPGA-Accelerated Models

Complete tutorial for creating models compatible with the OncologyAI FPGA platform

Prerequisites

Required software and hardware to develop FPGA models

Hardware Requirements

PYNQ Z1 Development Board (Zynq-7020)
MicroSD card (16GB+) with PYNQ image
Ethernet connection to host machine
Development PC with 16GB+ RAM

Software Requirements

Xilinx Vivado 2022.1+ (Design Suite)
Vitis HLS (for C/C++ to RTL)
Python 3.8+ with PYNQ library
Git for version control

FPGA Development Workflow

Understanding the end-to-end process of creating FPGA-accelerated models

Algorithm Design

Define your computation in C/C++

HLS Synthesis

Convert to RTL using Vitis HLS

Overlay Creation

Build bitstream in Vivado

Integration

Connect to OncologyAI platform

Why FPGA Acceleration?

FPGAs provide massive parallelism for computationally intensive tasks like cellular automaton simulations, Monte Carlo methods, and matrix operations. The PYNQ Z1 can achieve 100-1000x speedups compared to CPU-only implementations.

Project Structure

project-structure

bash

1oncology-fpga-model/
2├── hls/
3│   ├── src/
4│   │   └── my_accelerator.cpp    # HLS source code
5│   ├── include/
6│   │   └── my_accelerator.h      # Header files
7│   └── testbench/
8│       └── tb_my_accelerator.cpp # Testbench
9├── vivado/
10│   ├── constraints/
11│   │   └── pynq_z1.xdc           # Timing constraints
12│   └── project.tcl               # Vivado project script
13├── pynq/
14│   ├── overlays/
15│   │   ├── my_model.bit          # Bitstream
16│   │   └── my_model.hwh          # Hardware handoff
17│   └── notebooks/
18│       └── test_model.ipynb      # Test notebook
19└── backend/
20    └── handlers/
21        └── my_model_handler.py   # OncologyAI handler

PYNQ Z1 Specifications

Key hardware specifications for the target platform

Processing System

Dual-core ARM Cortex-A9 @ 650MHz
512MB DDR3 RAM
16GB MicroSD storage
Gigabit Ethernet

Programmable Logic

53,200 LUTs
106,400 Flip-Flops
630KB Block RAM
220 DSP Slices

Interfaces

AXI4 Master/Slave ports
AXI4-Lite for control
AXI4-Stream for data
Interrupt support

Ready to Build?

Start developing your FPGA-accelerated oncology model

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